1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit including dedicated test access port (TAP) cores.
2. Description of the Related Art
As a result of development in technology related to semiconductor fabrication and integrated circuits, System On a Chip (SOC) was proposed. Recently, as SOC design has been universally adopted, a plurality of cores are embedded in a single chip. To test these cores, a boundary scan method complying with the IEEE 1149.1 standard is usually used. A core having a boundary scan circuit is usually referred to as a TAP core. The IEEE 1149.1 standard defines using four test input pins and one test output pin to test a TAP core on a board.
A variety of designs for effectively testing a plurality of TAP cores embedded in a single chip have been proposed. Most general methods are ad-hoc TAP core integration methods as shown in FIGS. 1 and 2.
FIG. 1 is a diagram of a conventional integrated circuit realized according to a method using a dedicated test access port (TAP). Here, two TAP cores 11 and 13 are embedded in a single chip 100.
Referring to FIG. 1, each TAP core is connected to four test input pins and one test output pin. Specifically, input ports of the TAP core 11 are connected to four input pins TDI_A, TMS_A, TRST_A, and TCK_A of the chip 100, and an output port of the TAP core 11 is connected to an output pin TDO_A of the chip 100. Input ports of the TAP core 13 are connected to four input pins TDI_B, TMS_B, TRST_B, and TCK_B of the chip 100, and an output port of the TAP core 13 is connected to one input port of a multiplexer 15. The output port of the multiplexer is connected to another output pin TDO_B of the chip 100.
The input pins TDI_A, TMS_A, TRST_A, TCK_A, TDI_B, TMS_B, TRST_B, and TCK_B are pins defined by the IEEE 1149.1 standard. The input pins TDI_A and TDI_B are serial test data input pins. The input pins TMS_A and TMS_B are test mode selection signal input pins. The input pins TRST_A and TRST_B are test reset signal input pins. The input pins TCK_A and TCK_B are test clock signal input pins. The output pin TDO_B is a test data output pin.
An input port of a boundary scan register circuit 17 is connected to the data input pin TDI_B connected to an input port of the TAP core 13. An output port of the boundary scan register circuit 17 is connected to an input port of the multiplexer 15. The boundary scan register circuit 17 and the multiplexer 15 are connected to the TAP core 13 in FIG. 1. However, they may be connected to the TAP core 11. The boundary scan register circuit 17 can be controlled by the TAP core 11 or the TAP core 13.
The integrated circuit shown in FIG. 1 is advantageous in that the two TAP cores 11 and 13 can be independently controlled and tested by using four test input pins and one test output pin, which correspond to each of the TAP cores 11 and 13, during a chip test. In addition, only four input pins TDI_B, TMS_B, TRST_B, and TCK_B and one output pin TDO_B, which are related to the TAP core 13 connected to the boundary scan register circuit 17, are used on a board, thereby satisfying the IEEE 1149.1 standard.
However, on the board, only the TAP core 13 connected to the boundary scan register circuit 17 can be tested. Moreover, as the number of TAP cores increases, the number of input pins and output pins of the chip 100 increases.
FIG. 2 is a diagram of a conventional integrated circuit realized according to a method using pin sharing. Here, two TAP cores 21 and 23 are embedded in a single chip 200.
Referring to FIG. 2, four test input pins TDI, TMS, TRST, and TCK and one test output pin TDO of the chip 200 are shared by the two TAP cores 21 and 23. Input ports of the TAP core 21 and input ports of the TAP core 23 are commonly connected to the input pins TDI, TMS, TRST, and TCK. An output port of the TAP core 21 is connected to an input port of a multiplexer 25, and an output port of the TAP core 23 is connected to another input port of the multiplexer 25. An output port of the multiplexer 25 is connected to the output pin TDO of the chip 200.
The input pins TDI, TMS, TRST, and TCK are pins defined by the IEEE 1149.1 standard, as described in FIG. 1. The input pin TDI is a serial test data input pin. The input pin TMS is a test mode selection signal input pin. The input pin TRST is a test reset signal input pin. The input pin TCK is a test clock signal input pin. The output pin TDO is a test data output pin.
An input port of a boundary scan register circuit 27 is connected to the data input pin TDI shared by the TAP core 21 and the TAP core 23, and an output port of the boundary scan register circuit 27 is connected to a third input port of the multiplexer 25. The control port of the multiplexer 25 is connected to a control pin CONTROL of the chip 200. The multiplexer 25 selects one of the outputs of the TAP cores 21 and 23 and the boundary scan register circuit 27 in response to a signal applied to the control pin CONTROL. Here, the boundary scan register circuit 27 can be controlled by the TAP core 21 or the TAP core 23.
In the integrated circuit shown in FIG. 2, since the input pins TDI, TMS, TRST, and TCK and the output pin TDO are shared by the plurality of TAP cores 21 and 23, the number of the input pins and output pins of the chip 200 does not increase even when the number of TAP cores increases. However, the control pin CONTROL is additionally installed, which does not satisfy the IEEE 1149.1 standard.
If the control pin CONTROL is fixed to a predetermined value so that only a specified one of the TAP cores 21 and 23 can always be selected on a board, the IEEE 1149.1 standard can be satisfied. However, under these conditions, an unselected TAP core cannot be accessed.
To solve the above-described problems, it is an object of the present invention to provide a semiconductor integrated circuit satisfying the IEEE 1149.1 standard and allowing all test access port (TAP) cores embedded in a chip to be tested on a circuit board as well as on a chip.
In accordance with the invention, there is provided a semiconductor integrated circuit including a plurality of TAP cores, a boundary scan register circuit, a selection signal generating circuit, and a selector. The plurality of TAP cores share a predetermined number of input pins. The boundary scan register circuit has an input port connected to one of the input pins. The selection signal generating circuit has input ports connected to some of the input pins and generates selection signals for selecting one of the plurality of TAP cores and the boundary scan register circuit in response to signals input through the input ports connected to these input pins. The selector selects one of the outputs of the plurality of TAP cores and the boundary scan register circuit in response to the selection signals and outputs the selection to an output pin.
In one embodiment, the TAP cores share four input pins. The shared pins include a test data input pin, a test mode selection signal input pin, a test reset signal input pin, and a test clock signal input pin. An input port of the boundary scan register circuit can be connected to the test data input pin.
Input ports of the selection signal generating circuit can be connected to the test data input pin, the test reset signal input pin, and the test clock signal input pin. Alternatively, the input ports of the selection signal generating circuit can be connected to the test mode selection signal input pin, the test reset signal input pin and the test clock signal input pin. That is, instead of the test data input pin, the test mode selection signal input pin may be connected to the selection signal generating circuit. The selector selects one among the outputs of the plurality of TAP cores and the boundary scan register circuit in response to the selection signals and outputs the selection to an output pin.
In one embodiment, the selection signal generating circuit includes a shift register circuit for sequentially shifting data input through the test data input pin or the test mode selection signal input pin in response to a clock signal input through the test clock signal input pin, and a latch circuit for latching the data of the shift register circuit in response to a reset signal input through the test reset signal input pin and outputting the latched data as the selection signals.
In one embodiment, the selector is a multiplexer.